1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory comprising a plurality of different types of memory cells.
2. Description of the Background Art
A memory comprising a plurality of different types of memory cells is known in general. For example, Japanese Patent laying-Open No. 2001-167584 discloses such a memory.
The conventional memory disclosed in Japanese Patent Laying-Open No. 2001-167584 comprises 1T1C ferroelectric memory cells and SRAM (static random access memory) cells, while the ferroelectric memory cells and the SRAM cells share bit lines and a sense amplifier (read/write circuit) for reducing the chip size of the memory.
If the potential of any bit line shared by the corresponding ferroelectric and SRAM cells changes in an operation of reading or writing data from or in the corresponding SRAM cell in the aforementioned memory disclosed in Japanese Patent Laying-Open No. 2001-167584, the potential change of the bit line is transmitted to the corresponding ferroelectric memory cell. When the potential change of the bit line is transmitted to the ferroelectric memory cell in this manner, the quantity of polarization of a ferroelectric capacitor constituting the ferroelectric memory cell may be reduced by disturbance or data held in the ferroelectric capacitor may be destroyed. Therefore, the conventional memory disclosed in Japanese Patent Laying-Open No. 2001-167584 must employ ferroelectric memory cells having transistors for suppressing transmission of potential change of corresponding bit lines to ferroelectric capacitors. In the conventional memory disclosed in Japanese Patent Laying-Open No. 2001-167584, therefore, it is disadvantageously difficult to employ small-sized ferroelectric memory cells such as crosspoint memory cells, having no transistors, formed by arranging ferroelectric films between bit lines and word lines. Consequently, it is disadvantageously difficult to attain an effect of reducing the chip size by reducing the memory cell size in addition to the effect of reducing the chip size by sharing the sense amplifier (read/write circuit) between the ferroelectric memory cells and the SRAM memory cells.